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SAF7115
Multistandard video decoder with super-adaptive comb filter, scaler and VBI data read-back via I2C-bus
Rev. 01 -- 15 October 2008 Product data sheet
1. General description
The SAF7115 is a video capture device that, due to its improved comb filter performance and 10-bit video output capabilities, is suitable for various applications such as In-car video reception, In-car entertainment or In-car navigation. The SAF7115 is a combination of a two channel analog preprocessing circuit and a high performance scaler. The two channel analog preprocessing circuit includes source-selection, an anti-aliasing filter and Analog-to-Digital Converter (ADC) per channel, an automatic clamp and gain control, two Clock Generation Circuits (CGC1 and CGC2) and a digital multi standard decoder that contains two-dimensional chrominance/luminance separation utilizing an improved adaptive comb filter. The high performance scaler has variable horizontal and vertical up and down scaling and a brightness/contrast/saturation control circuit. The decoder is based on the principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and NTSC signals into ITU-601 compatible color component values. The SAF7115 accepts CVBS or S-video (Y/C) from TV or VCR sources as analog inputs, including weak and distorted signals. The expansion port (X-port) for digital video (bi-directional half duplex, D1 compatible) can be used to either output unscaled video using 10-bit or 8-bit dithered resolution or to connect to other external digital video sources for reuse of the SAF7115 scaler features. The enhanced image port (I-port) of the SAF7115 supports 8-bit and 16-bit wide output data with auxiliary reference data for interfacing, e.g. with VGA controller applications. It is also possible to output video in square pixel formats accompanied by a square pixel clock of the appropriate frequency. The SAF7115 also incorporates provisions for capturing the serially coded data in the Vertical Blanking Interval (VBI-data) of several standards in parallel. Three basic options are available to transfer the VBI data to other devices:
* Capturing raw video samples, after interpolation to the required output data rate,
using the scaler and transferring the data to a device connected to the I-port
* Slicing the VBI data using the built-in VBI data slicer (data recovery unit) and
transferring the data to a device connected to the I-port
* Slicing the VBI data using the built-in VBI data slicer and reading out the sliced data
through the I2C-bus (for several slow VBI data type standards only)
NXP Semiconductors
SAF7115
Multistandard video decoder
The SAF7115 incorporates a frame locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a frame, or a set of fields. This prevents the loss of synchronization between video and audio, during capture or playback. Furthermore, there is an option to use a second analog onboard PLL to enhance this audio clock to a low jitter frame locked audio clock. The SAF7115 is controlled through the I2C-bus with full write/read capability for all programming registers and a bit-rate of up to 400 kbit/s. See Ref. 1 for a detailed register description, pin strapping and applications.
2. Features
2.1 Video acquisition
I Six analog inputs, internal analog source selectors, e.g. (6 x CVBS) or (2 x Y/C and 2 x CVBS) or (1 x Y/C and 4 x CVBS) I Two differential (bi-phase) video inputs as an alternative I Two built-in analog anti-alias filters I Two improved 9-bit CMOS ADCs in differential CMOS style at two-fold ITU-656 oversampling (27 MHz) I Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel I Automatic Clamp Control (ACC) for CVBS, Y and C I Switchable white peak control. Two 9-bit video CMOS ADCs, digitized CVBS or Y/C I Signals are available on the expansion port (X-port) I Requires only one crystal (32.11 MHz or 24.576 MHz) for all standards I Independent gain and offset adjustments for raw data path
2.2 Comb filter video decoder
I Digital PLL for synchronization and clock generation from all standard and non-standard video sources e.g. consumer grade Video Tape Recorders (VTR) I Automatic detection of 50 Hz and 60 Hz field frequencies I Automatic recognition of all common broadcast standards I Enhanced horizontal and vertical sync detection I Luminance and chrominance signal processing for: N PAL BGDHIN N Combination-PAL N N PAL M N NTSC M N NTSC-Japan N NTSC 4.43 N SECAM (50 Hz/60 Hz) I PAL delay line for correcting PAL phase errors I Improved 2/4-line comb filter for two dimensional chrominance/luminance-separation operating with adaptive comb filter parameters. N Increased luminance and chrominance bandwidth for all PAL and NTSC-standards N Reduced cross color and cross luminance artefacts
SAF7115_1 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
2 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
I Independent Brightness Contrast Saturation (BCS) - adjustment for decoder part I User programmable sharpness control I Detection of copy protected input signals: N According to Macrovision standard N Indicating the level of protection I Automatic TV/VCR detection I 10-bit wide video output at comb filter video decoder I X-port video output either as: N Noise shaped 8-bit ITU-656 video or N Full 10-bit ITU-656 interface (DC-performance 9-bit)
2.3 Video scaler
I Horizontal and vertical down-scaling and up-scaling to randomly sized windows I Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (note: H and V zoom are restricted by the transfer data rates) I Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy) I Conversion to square pixel format I Generation of a video output stream with improved synchronization grid at the I-port I Two independent programming sets for scaler part, to define two regions (e.g. for different scaling for VBI and active picture) per field or sequences over frames I Fieldwise switching between decoder part and expansion port (X-port) input I Brightness, contrast and saturation controls for scaled outputs
2.4 VBI data slicer
I Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization, e.g.: N WST525/WST625 (CCST) N VPS N US/European Close Caption (CC) N WSS525 (CGMS), WSS625 N US NABTS N VITC 525/VITC 625 N Gemstar 1x N Gemstar 2x N Moji 2C-bus read-back of the following decoded data types: II N US Close Caption (CC) N European Close Caption (CC) N WSS525 (CGMS) N WSS625 (CGMS) N Gemstar 1x N Gemstar 2x
SAF7115_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
3 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
2.5 Clock generation
I On-chip line locked clock generation according ITU-601 I Generation of a frame locked audio master clock to support a constant number of audio clocks per video field I Second onboard analog Phase-Locked Loop (PLL) to be used for: N On-chip line locked square pixel clock generation for PAL and NTSC square pixel video output or N The generation of a low jitter frame locked audio clock from the audio master clock through reuse of the analog square pixel PLL. The audio clock frequencies supported are 256 x fs, 384 x fs and 512 x fs (fs = 32 kHz, 44.1 kHz or 48 kHz)
2.6 General features
I CMOS 3.3 V device with 5 V tolerant digital inputs and I/O ports I Programming through serial I2C-bus, full read-back ability by an external controller, bit-rate up to 400 kbit/s I Software controlled power saving stand-by modes I Boundary Scan Test circuit complies to the IEEE Std. 1149.b1-1994
3. Applications
I I I I General industrial video applications In-car TV reception In-car entertainment In-car navigation platforms
4. Ordering information
Table 1. Ordering information Package Name SAF7115HW SAF7115ET HTQFP100 TFBGA160 Description plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad plastic thin fine-pitch ball grid array package; 160 balls Version SOT638-1 SOT1016-1 Type number
SAF7115_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
4 of 35
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Product data sheet Rev. 01 -- 15 October 2008
(c) NXP B.V. 2008. All rights reserved. SAF7115_1
5. Block diagram
NXP Semiconductors
LLC2 RTS0 LLC RTC0 RTS1
XDQ XCLK XPD[7:0]
XRH XRDY XRV XTRI
HPD[7:0]
SDA SCL
TEST[9:0]
AGND AI11 AI12 AI21 AI22 AI23 AI24 AOUT AI1D AI2D CLOCK GENERATION AND POWER-ON CONTROL ANALOG DUAL ADC
RT OUT
EXPANSION PORT PIN MAPPING
I/O CONTROL
I2C-BUS
X PORT I/O FORMATTING
SAF7115
VIDEO/TEXT ARBITER
DIGITAL DECODER WITH ADAPTIVE COMB FILTER
FIR PREFILTER PRESCALER AND SCALER BCS
LINE FIFO BUFFER
VERTICAL SCALING
HORIZONTAL FINE (PHASE) SCALING
IPD[7:0] VIDEO FIFO 32 TO 8(16) MUX TEXT FIFO IDQ IGPH IMAGE PORT MAPPING IGPV IGP0 IGP1
GENERAL PURPOSE VBI DATA SLICER
EVENT CONTROLLER
PULSE GENERATOR
RESO_N CE XTOUT XTALI XTALO
ICLK
PLL2
CGC2
ITRDY FRAME LOCKED AUDIO CLOCK PLL AUDIO CLOCK GENERATION PROGRAMMING REGISTER ARRAY A/B REGISTER MUX BOUNDARY SCAN TEST ITRI
Multistandard video decoder
VDDA(XTAL) VSSA(XTAL)
AXMCLK ALRCLK VDDD(CORE) VDDD(IO) AMCLK ASCLK
VDDA0 VDDA2 VSSD(IO) VDDA1 VSSD(CORE)
VSSA
TDO TRST_N TMS TCK TDI 001aag268
SAF7115
5 of 35
Fig 1.
Block diagram
NXP Semiconductors
SAF7115
Multistandard video decoder
6. Pinning information
6.1 Pinning
ball A1 index area
SAF7115ET
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1
75
SAF7115HW
25 26 50
51
A B C D E F G H J K L M N P
001aah235
100
76
001aag269
Transparent top view
a. HTQFP100 Fig 2. Pin configuration Table 2. Pin 1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73
b. TFBGA160
Pin allocation table (HTQFP100) Pin 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 Symbol TDO[1] XTALO AI24 AI22 AI12 AOUT VSSD(IO) RESO_N RTS0 VSSD(CORE) ITRDY IDQ VSSD(IO) IPD7 VDDD(CORE) IPD0 HPD5 HPD2 TEST2 Pin 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 67 71 75 Symbol TDI[1] XTALI VDDA2 VSSA AI1D VDDA0 CE SCL RTS1 ASCLK VDDD(CORE) ITRI VDDD(IO) IPD6 IPD3 VSSD(CORE) HPD4 HPD1 VDDD(IO) Pin 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 Symbol XTOUT VDDA(XTAL) AI23 AI21 AI11 VSSA LLC SDA RTCO[1] ALRCLK TEST0 IGP0 IGPV IPD5 IPD2 HPD7 VDDD(CORE) HPD0 VSSD(IO)
Symbol VDDD(IO) VSSA(XTAL) VSSA AI2D VDDA1 AGND VDDD(IO) LLC2 VDDD(CORE) AMCLK AMXCLK ICLK IGP1 IGPH IPD4 IPD1 HPD6 HPD3 TEST1
SAF7115_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
6 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
Pin allocation table (HTQFP100) ...continued Pin 78 82 86 90 94 98 Symbol TEST4 XPD6 XPD3 XPD0 XCLK TCK[1] Pin 79 83 87 91 95 99 Symbol TEST5 VDDD(CORE) XPD2 XRV XDQ TMS[1] Pin 80 84 88 92 96 Symbol XTRI XPD5 VSSD(CORE) XRH XRDY
Table 2. Pin 77 81 85 89 93 97
[1]
Symbol TEST3 XPD7 XPD4 XPD1 VDDD(CORE) TRST_N[1]
See Table 4.
100 VSSD(IO)
Table 3. Pin A1 A5 A9 Row A
Pin allocation table (TFBGA160)[1] Pin A2 A6 Symbol TMS[2] XRH Pin A3 A7 B3 B7 Symbol TRST_N[2] XPD0 TCK[2] XPD1 Pin A4 A8 B4 B8 Symbol XRDY VSSD(CORE) XDQ XPD2 -
Symbol VDDD(IO) XCLK XPD3
A10 XPD5 A14 VDDD(IO) B2 B6 TDO[2] XRV
A11 XPD6
A12 XTRI
A13 TEST4 Row B B1 B5 B9 XTOUT VDDD(CORE) XPD4
B10 VDDD(CORE) B14 TEST3 C2 D2 D7 TDI[2] VSSA(XTAL) VSSD(IO)
B11 XPD7
B12 TEST5
B13 TEST2 Row C C1 D1 D6 XTALO XTALI VSSD(IO)
C13 HPD0 D4 D8 VSSD(IO) VSSD(IO)
C14 TEST1 D5 D9 VSSD(IO) VSSD(IO)
Row D
D10 VSSD(IO) Row E E1 E6 VDDA(XTAL) VSSD(IO)
D11 VSSD(IO) E2 E7 VSSA VSSD(IO)
D13 HPD2 E4 E8 VSSD(IO) VSSD(IO)
D14 HPD1 E5 E9 VSSD(IO) VSSD(IO)
E10 VSSD(IO) Row F F1 F6 VDDA2 VSSD(IO)
E11 VSSD(IO) F2 F7 AI24 VSSD(IO)
E13 VDDD(CORE) F4 F8 VSSD(IO) VSSD(IO)
E14 HPD3 F5 F9 VSSD(IO) VSSD(IO)
F10 VSSD(IO) Row G G1 G6 AI23 VSSD(IO)
F11 VSSD(IO) G2 G7 AI2D VSSD(IO)
F13 HPD5 G4 G8 VSSD(IO) VSSD(IO)
F14 HPD4 G5 G9 VSSD(IO) VSSD(IO)
G10 VSSD(IO) Row H H1 H6
SAF7115_1
G11 VSSD(IO) H2 H7 VSSA VSSD(IO)
G13 HPD7 H4 H8 VSSD(IO) VSSD(IO)
G14 HPD6 H5 H9 VSSD(IO) VSSD(IO)
(c) NXP B.V. 2008. All rights reserved.
AI22 VSSD(IO)
Product data sheet
Rev. 01 -- 15 October 2008
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NXP Semiconductors
SAF7115
Multistandard video decoder
Pin allocation table (TFBGA160)[1] ...continued Pin Symbol Pin Symbol Pin Symbol H11 VSSD(IO) J2 J7 J11 K2 K7 VDDA1 VSSD(IO) VSSD(IO) AI1D VSSD(IO) H13 IPD0 J4 J8 J13 K4 K8 VSSD(IO) VSSD(IO) IPD2 VSSD(IO) VSSD(IO) H14 VSSD(CORE) J5 J9 J14 K5 K9 VSSD(IO) VSSD(IO) IPD1 VSSD(IO) VSSD(IO)
Table 3. Pin
Symbol
H10 VSSD(IO) Row J J1 J6 J10 K1 K6 AI21 VSSD(IO) VSSD(IO) AI12 VSSD(IO)
Row K
K10 VSSD(IO) Row L L1 L6 AI11 VSSD(IO)
K11 VSSD(IO) L2 L7 AGND VSSD(IO)
K13 VDDD(CORE) L4 L8 TEST6 VSSD(IO)
K14 IPD3 L5 L9 TEST7 VSSD(IO)
L10 TEST8 Row M M1 N1 N5 N9 AOUT VSSA VDDD(CORE) AMXCLK
L11 TEST9 M2 N2 N6 VDDA0 CE RTS1
L13 IPD5 M13 IPD7 N3 N7 P3 P7 LLC2 AMCLK RESO_N VSSD(CORE) -
L14 IPD4 M14 IPD6 N4 N8 P4 P8 SCL ASCLK SDA ALRCLK -
Row N
N10 VDDD(CORE) N14 IGPH P2 P6 LLC RTCO[2]
N11 ICLK
N12 ITRI
N13 IGP1 Row P P1 P5 P9 VDDD(IO) RTS0 ITRDY
P10 TEST0 P14 VDDD(IO)
P11 IDQ
P12 IGP0
P13 IGPV
[1] [2]
i.c.: internally connected; do not connect See Table 4.
6.2 Pin description
Table 4. Symbol Pin description Pin HTQFP100 Supplies (analog) VDDA0 VDDA1 VDDA2 VDDA(XTAL) VSSA VSSA(XTAL) 23 17 11 8 9, 15 and 24 5 M2 J2 F1 E1 E2, H2 and N1 D2 P P P P P P analog supply voltage 0[2] analog supply voltage 1[3] analog supply voltage 2[4] crystal analog supply voltage analog ground supply voltage crystal analog ground supply voltage TFBGA160 Type[1] Description
SAF7115_1
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Product data sheet
Rev. 01 -- 15 October 2008
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NXP Semiconductors
SAF7115
Multistandard video decoder
Table 4. Symbol
Pin description ...continued Pin HTQFP100 TFBGA160 P I/O digital supply voltage core digital supply voltage Type[1] Description
Supplies (digital) VDDD(IO) VDDD(CORE) 1, 25, 51 and A1, A14, P1 75 and P14
33, 43, 58, B5, B10, P 68, 83 and 93 E13, K13, N5 and N10 38, 63 and 88 A8, H14 and P7 26, 50, 76 and 100 D4 to D11, E4 to E11, F4 to F11, G4 to G11, H4 to H11, J4 to J11, K4 to K11 and L6 to L9 L2 J1 H1 G1 F2 G2 L1 K1 K2 M1 N4 P4 N2 P3 P8 P P
VSSD(CORE) VSSD(IO)
core digital ground supply voltage I/O digital ground supply voltage
Analog inputs AGND AI21 AI22 AI23 AI24 AI2D AI11 AI12 AI1D AOUT I2C-bus SCL SDA CE RESO_N Audio clock ALRCLK 40 (I/) O/st/pd audio left/right clock output: can be strapped to supply through a 3.3 k resistor indicating that the default 24.576 MHz crystal (internal pull-down) has been replaced by a 32.11 MHz crystal O I O audio master clock output audio master external clock input audio serial clock output 31 32 27 30 I (/O)/od I (/O)/od I/pu O serial clock input (/output) with inactive output path serial data input (/output) chip enable or reset input (with internal pull-up) reset output (active low) 21 16 14 12 10 13 20 18 19 22 P AI AI AI AI AI AI AI AI AO analog signal ground reference for all AIx inputs analog input 21 analog input 22 analog input 23 analog input 24 differential input for ADC channel 2 (pins AI24, AI23, AI22 and AI21)[5] analog input 11 analog input 12 differential input for ADC channel 1 (pins AI12 and AI11)[5] analog test output (do not connect)
Analog output
General control
AMCLK AMXCLK ASCLK
37 41 39
N7 N9 N8
SAF7115_1
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Product data sheet
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NXP Semiconductors
SAF7115
Multistandard video decoder
Table 4. Symbol
Pin description ...continued Pin HTQFP100 TFBGA160 P6 N6 P5 (I/) O/st/pd real time control output[6] O O real time status or sync information, controlled by subaddresses 11h and 12h real time status or sync information, controlled by subaddresses 11h and 12h line-locked system clock output (27 MHz nominal), for backward compatibility; use pin XCLK for new applications line locked 1/2 clock output (13.5 MHz nominal) for backward compatibility; do not use for new applications input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of external oscillator with TTL compatible square wave clock signal 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if pin XTALI is driven by an external single-ended oscillator crystal oscillator output signal, auxiliary signal test clock for boundary scan test (with internal pull-up)[7] test data input for boundary scan test (with internal pull-up)[7] test data output for boundary scan test[7] test mode select for boundary scan test or scan test (with internal pull-up)[8] test reset for boundary scan test (active LOW with internal pull-up); for board design without boundary scan connect TRST_N to `ground', e.g. through VSSD(CORE) or VSSD(IO)[8] do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing do not connect, reserved for future extensions and for testing clock output signal for image port or optional asynchronous back end clock input output data qualifier for image port (optional: gated clock output) general purpose output signal 1; image port (controlled by subaddresses 84h and 85h); same functions as pin IGP0
(c) NXP B.V. 2008. All rights reserved.
Type[1]
Description
Real time signals RTCO RTS1 RTS0 Clocks LLC LLC2 XTALI 28 29 7 P2 N3 D1 O O I 36 35 34
XTALO XTOUT TCK TDI TDO TMS TRST_N
6 4 98 3 2 99 97
C1 B1 B3 C2 B2 A2 A3
O O I/pu I/pu O I/pu I/pu
Boundary scan test
Test interface TEST9 TEST8 TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 ICLK IDQ IGP1 79 78 77 74 73 44 45 46 49 L11 L10 L5 L4 B12 A13 B14 B13 C14 P10 N11 P11 N13 I/pd AI AI I/pu I/pu O I/pu I/pu I/pu O I/O O O
Image port (I-port)
SAF7115_1
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NXP Semiconductors
SAF7115
Multistandard video decoder
Table 4. Symbol IGP0 IGPH IGPV IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0 ITRDY ITRI
Pin description ...continued Pin HTQFP100 48 53 52 54 55 56 57 59 60 61 62 42 47 TFBGA160 P12 N14 P13 M13 M14 L13 L14 K14 J13 J14 H13 P9 N12 O O O O O O O O O O O I/pu I (/O)/pd general purpose output signal 0; image port (controlled by subaddresses 84h and 85h) multipurpose horizontal reference output signal; image port (controlled by subaddresses 84h and 85h) multipurpose vertical reference output signal; image port (controlled by subaddresses 84h and 85h) MSB of image port data output MSB - 1 of image port data output MSB - 2 of image port data output MSB - 3 of image port data output MSB - 4 of image port data output MSB - 5 of image port data output MSB - 6 of image port data output LSB of image port data output target ready input, image port (with internal pull-up) image port output control signal, affects all I-port pins including ICLK, enable and active polarity is under software control (bits IPE in subaddress 87h) output path used for testing: scan output clock I/O expansion port data qualifier I/O expansion port MSB of expansion-port data: in 8-bit video output mode: this signal represents the video bit 7; in 10-bit video output mode: this signal represents the video bit 9 MSB - 1 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 6; in 10-bit video output mode: this signal represents the video bit 8 MSB - 2 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 5; in 10-bit video output mode: this signal represents the video bit 7 MSB - 3 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 4; in 10-bit video output mode: this signal represents the video bit 6 MSB - 4 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 3; in 10-bit video output mode: this signal represents the video bit 5 MSB - 5 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 2; in 10-bit video output mode: this signal represents the video bit 4 MSB - 6 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 1; in 10-bit video output mode: this signal represents the video bit 3 expansion-port data: in 8-bit video output mode: this signal represents the video bit 0 (LSB); in 10-bit video output mode: this signal represents the video bit 2 Type[1] Description
Expansion port (X-port) XCLK XDQ XPD7 94 95 81 A5 B4 B11 I/O I/O I/O
XPD6
82
A11
I/O
XPD5
84
A10
I/O
XPD4
85
B9
I/O
XPD3
86
A9
I/O
XPD2
87
B8
I/O
XPD1
89
B7
I/O
XPD0
90
A7
I/O
SAF7115_1
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Product data sheet
Rev. 01 -- 15 October 2008
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NXP Semiconductors
SAF7115
Multistandard video decoder
Table 4. Symbol XRDY XRH XRV XTRI
Pin description ...continued Pin HTQFP100 96 92 91 80 TFBGA160 A4 A6 B6 A12 O I/O I/O I/pd task flag or read signal from scaler, controlled by bit XRQT (subaddress 83h) horizontal reference I/O expansion-port: in 10-bit video output mode: this signal represents the video bit 1 vertical reference I/O expansion-port: in 10-bit video output mode: this signal represents the video bit 0 (LSB) X-port output control signal, affects all X-port pins (XPD[7:0], XRH, XRV, XDQ and XCLK) enable and active polarity is under software control (bits XPE in subaddress 83h) MSB of host port data I/O, carries CbCr chrominance information in 16-bit video I/O modes MSB - 1 of host port data I/O, carries CbCr chrominance information in 16-bit video I/O modes MSB - 2 of host port data I/O, carries CbCr chrominance information in 16-bit video I/O modes MSB - 3 of host port data I/O, carries CbCr chrominance information in 16-bit video I/O modes MSB - 4 of host port data I/O, carries CbCr chrominance information in 16-bit video I/O modes MSB - 5 of host port data I/O, carries CbCr chrominance information in 16-bit video I/O modes MSB - 6 of host port data I/O, carries CbCr chrominance information in 16-bit video I/O modes LSB of host port data I/O, carries CbCr chrominance information in 16-bit video I/O modes Type[1] Description
Host port (H-port) HPD7 HPD6 HPD5 HPD4 HPD3 HPD2 HPD1 HPD0 64 65 66 67 69 70 71 72 G13 G14 F13 F14 E14 D13 D14 C13 I/O I/O I/O I/O I/O I/O I/O I/O
[1] [2] [3] [4] [5]
A = analog, I = input, O = output, P = power, st = strapping, pu = pull-up, pd = pull-down, od = open-drain. For CGC1 and CGC2. For analog inputs AI1x. For analog inputs AI2x. For normal operation connect pins AI1D and AI2D to ground through a capacitor. In principle both analog input stages can operate in differential mode, too, depending on the application. This may be interesting for differential video (CVBS). Please contact NXP for more information. This contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier phase and frequency and PAL sequence (according to RTC level 3.1, refer to external document RTC Functional Specification for details), can be strapped to supply through a 3.3 k resistor to change the default I2C-bus read and write addresses from 42h and 43h (internal pull-down) to 40h and 41h. According to the IEEE1149.b1-1994 standard pins TDI and TMS are input pins with an internal pull-up transistor and TDO is a 3-state output pin. Pins TCK and TRST_N are also built with internal pull-up. This pin provides easy initialization of BST circuitry. Pin TRST_N can be used to force the Test Access Port (TAP) controller to the test-logic-reset state (normal operation) at once.
[6]
[7] [8]
SAF7115_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
12 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
7. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and grounded (0 V); all supply pins connected together. Symbol VDDA0 VDDA1 VDDA2 VDDA(XTAL) VDDD(CORE) VDDD(IO) VI(a) Vi VI(D) VSS Tstg Tamb Vesd Parameter analog supply voltage 0 analog supply voltage 1 analog supply voltage 2 crystal analog supply voltage core digital supply voltage I/O digital supply voltage analog input voltage input voltage digital input voltage ground supply voltage difference storage temperature ambient temperature electrostatic discharge voltage human body model, all pins charged device model, corner pins charged device model, all other pins
[1] [2] [3] Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < VDDD < 3.6 V. Class 2 according to EIA/JESD22-114. Class C3B according to AEC-Q100-011.
[2] [3] [3]
Conditions for CGC1 and CGC2 for analog inputs AI1x for analog inputs AI2x
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
Max +4.6 +4.6 +4.6 +4.6 +4.6 +4.6 +4.6 +4.6 +5.5 100 +150 +85 2000 750 500
Unit V V V V V V V V V mV C C V V V
at pins XTALI, SDA and SCL outputs in 3-state
[1]
-0.5 -0.5 -0.5 -65 -40 -
VDDx + 0.5 V
8. Thermal characteristics
Table 6. Symbol Rth(j-a) Thermal characteristics Parameter Conditions SAF7115ET SAF7115HW
[1]
[1] [2]
Typ 23 35
Unit K/W K/W
thermal resistance from junction to ambient in free air
The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly and use maximum areas for power and ground planes in the application PCB. In order to meet the specified Rth(j-a) value the exposed die pad of the package has to be soldered directly to the ground layer of the application PCB. The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly and use maximum areas for power and ground planes in the application PCB. The Rth(j-a) value is calculated for a 4 layer PCB (100 x 100 mm2) with at least 50 plated through-hole-vias at the center of the package (large ground area). This calculation assumes 80 % coverage for power and ground metal layers and a natural convection flow at top and bottom sides of the PCB. Maximum ball temperature then is 110 C, assuming ambient temperature Tamb(max) = 85 C.
[2]
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9. Characteristics
Table 7. Characteristics VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 C; timings and levels refer to drawings and conditions illustrated in Figure 3 and Figure 4; unless otherwise specified. Symbol Supplies VDDA0 VDDA1 VDDA2 VDDA(XTAL) analog supply voltage 0 for CGC1 and CGC2 analog supply voltage 1 for analog inputs AI1x analog supply voltage 2 for analog inputs AI2x crystal analog supply voltage 3.1 3.1 3.1 3.1 3.0 3.0 VDDAx = 3.3 V; bits AOSL1 and AOSL0 = 0b CVBS mode Y/C mode IDDD P digital supply current power dissipation X-port 3-state; 8-bit I-port out digital part; open pin AOUT analog part; VDDAx = 3.3 V CVBS mode Y/C mode analog and digital parts CVBS mode Y/C mode power-down mode power-save mode Analog part Vi(p-p) peak-to-peak input voltage for normal video levels 1 V (p-p), -3 dB termination 18 to 56 and AC coupling required; coupling capacitor is 47 nF VI = 1 V DC clamping current off fi < 5 MHz at -3 dB amplifier plus anti-alias filter bypassed 0.7 V
[2] [3] [1]
Parameter
Conditions
Min
Typ 3.3 3.3 3.3 3.3 3.3 3.3
Max 3.5 3.5 3.5 3.5 3.6 3.6
Unit V V V V V V
VDDD(CORE) core digital supply voltage VDDD(IO) IDDA I/O digital supply voltage analog supply current
-
81 142 108 356 267 468 623 825 7 115
-
mA mA mA mW mW mW mW mW mW mW
ICL |Zi| Ci cs B dif
clamping current input impedance input capacitance channel separation bandwidth differential phase
200 -
8 7 2
10 -50 -
A k pF dB MHz deg
9-bit analog-to-digital converters
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Table 7. Characteristics ...continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 C; timings and levels refer to drawings and conditions illustrated in Figure 3 and Figure 4; unless otherwise specified. Symbol Gdif fclk(ADC) DLEDC ILEDC GADC VIL Parameter differential gain ADC clock frequency DC differential linearity error DC integral linearity error ADC gain difference LOW-level input voltage pins SCL and SDA any other pin, including pin XTALI VIH HIGH-level input voltage pins SCL and SDA pin XTALI any other pin ILI IL(I/O) Ci Digital VOL input leakage current leakage current (I/O) input capacitance outputs[6] LOW-level output voltage pin SDA at 3 mA sink current all digital clocks for all other digital outputs VOH HIGH-level output voltage output load capacitance cycle time duty cycle rise time fall time delay time pin LLC pin LLC2 tr tf td for tCLKH/Tcy; CL = 40 pF 0.2 V to VDDD(IO) - 0.2 V VDDD(IO) - 0.2 V to 0.2 V between LLC and LLC2: measured at 1.5 V; CL = 25 pF 50 Hz field 60 Hz field all digital output pins 0 0 2.4 0.4 0.6 0.4 VDDD(IO) + 0.5 V V V V I/O at high-impedance
[4]
Conditions amplifier plus anti-alias filter bypassed
Min 25.4 -0.5 -0.3 0.7 x VCC(I2C-bus) 2.0 2.0 -
Typ 2 - 0.7 1 3 -
Max 28.6 +0.3 x VCC(I2C-bus) +0.8
Unit % MHz LSB LSB % V V
Digital inputs
[5]
[5]
[5]
VCC(I2C-bus) + 0.5 V VDDA(XTAL) + 0.3 5.5 1 10 8 V V A A pF
Clock output timing (LLC and LLC2)[7] Co(L) Tcy 15 35 70 40 -4 +1 50 39 78 60 5 5 +8 pF ns ns % ns ns ns
Horizontal PLL fhl(nom) fhl/fhl(nom) nominal horizontal line frequency horizontal line frequency deviation 15625 15734 5.7 Hz Hz %
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Table 7. Characteristics ...continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 C; timings and levels refer to drawings and conditions illustrated in Figure 3 and Figure 4; unless otherwise specified. Symbol fsubc(nom) Parameter nominal subcarrier frequency Conditions PAL BGHI NTSC M PAL M PAL N fsubc(lock-in) subcarrier lock-in frequency Expansion port (X-port) output timing with XCLK clock output Co(L) Tcy tr tf output load capacitance cycle time duty cycle rise time fall time XCLK output for tXCLKH/Tcy 0.6 V to 2.6 V 2.6 V to 0.6 V 15 35 35 50 39 65 5 5 pF ns % ns ns Min 400 Typ Max Unit Hz Hz Hz Hz Hz Subcarrier PLL 4433619 3579545 3575612 3582056 -
Data and control signal output timing X-port including RT-port, related to XCLK output (for XPCK[1:0] 83h[5:4] = 01b)[7] Co(L) th(Q) tPD output load capacitance data output hold time propagation delay from positive edge of XCLK output XCLK input for tXCLKH/Tcy
[8] [8]
15 2 -
-
50 23
pF ns ns
Expansion port (X-port) input timing with XCLK clock input Tcy tr tf tsu(D) th(D) th(Q) tPD cycle time duty cycle rise time fall time data input set-up time data input hold time data output hold time propagation delay from positive edge of XCLK input
[9] [9] [10] [10]
31 40 6 -
50 3 23
45 60 5 5 6 -
ns % ns ns ns ns ns ns
Data and control signal input timing X-port, related to XCLK input (for XPCK[1:0] 83h[5:4] = 11b);
Image port (I-port) output timing with ICLK clock output Co(L) Tcy tr tf Tcy output load capacitance cycle time duty cycle rise time fall time cycle time duty cycle for tICLKH/Tcy for tICLKH/Tcy; CL = 40 pF 0.6 V to 2.6 V 2.6 V to 0.6 V 15 31 35 31 40 50 50 90 65 5 5 100 60 pF ns % ns ns ns %
Image port (I-port) output timing with ICLK clock input
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Table 7. Characteristics ...continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 C; timings and levels refer to drawings and conditions illustrated in Figure 3 and Figure 4; unless otherwise specified. Symbol tr tf Co(L) th(Q) tPD tsu(D) th(D) Co(L) th(Q) tPD Parameter rise time fall time Conditions 0.6 V to 2.6 V 2.6 V to 0.6 V Min 15
[11] [11]
Typ -
Max 5 5 50 23 -2 50 23
Unit ns ns pF ns ns ns ns pF ns ns
Data and control signal output timing I-port, related to ICLK output (for IPCK[1:0] 87h[5:4] = 11b) output load capacitance at all outputs data output hold time propagation delay data input set-up time data input hold time output load capacitance at all outputs data output hold time propagation delay from positive edge of LLC output
[11] [11]
3 18 15 3 -
Data and control signal input timing I-port, related to ICLK output (for IPCK[1:0] 87h[5:4] = 11b)
[12] [12]
Data and control signal output timing I-port, related to ICLK input (for IPCK[1:0] 87h[5:4] = 11b)
Data and control signal input timing I-port, related to ICLK input (for IPCK[1:0] 87h[5:4] = 01b) tsu(D) th(D) Co(L) tr tf
[1] [2] [3] [4] [5] [6] [7] [8] [9]
data input set-up time data input hold time output load capacitance rise time fall time 0.6 V to 2.6 V 2.6 V to 0.6 V
[12] [12]
12 15 -
-
2 50 5 5
ns ns pF ns ns
AMCLK clock output
This setting connects pin AOUT to ground. Controlled through chip enable input (CE) from normal operation mode at typical supply voltage of VDDD = VDDA = 3.3 V. I2C-bus controlled through subaddress 88h set to xx00 1011b. The ADC gain difference is G ADC = ----------------------------------------------- - 1 x 100 . - minimum deviation
maximum deviation
VCC(I2C-bus) is the external supply voltage of the I2C-bus (3.3 V or 5 V). The levels must be measured with load circuits; 1.2 k at 3 V (TTL load); CL = 50 pF. The effects of rise and fall times are included in the calculation of th(Q) and tPD. Timings and levels refer to drawings and conditions illustrated in Figure 3 and Figure 4. Valid for outputs: XPD [7:0], XRH, XRV, XDQ, RTS0, RTS1, RTCO Valid for inputs: XPD [7:0], HPD [7:0], XRH, XRV, XDQ
[10] Valid for output: XRDY [11] Valid for outputs: IPD [7:0], HPD [7:0], IGPH, IGPV, IDQ, IGP1, IGP0 [12] Valid for input: ITRDY
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Tcy t XCLKH 2.6 V clock output XCLK 1.5 V 0.6 V t su(D) t h(D) data and control inputs (X port)(1) 2.0 V not valid 0.8 V t PD t h(Q) data and control outputs X port(2) 2.4 V tf tr
0.6 V
001aae770
(1) See Table 7. (2) See Table 7.
Fig 3. X-port input and output timing
Tcy t ICLKH clock input or output ICLK 2.6 V 1.5 V 0.6 V tf t PD t h(Q) data and control outputs I port(1) 2.4 V tr
0.6 V
001aae771
(1) See Table 7.
Fig 4. I-port output timing, also valid for IX-port and H-port
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Table 8. Symbol fxtal(nom) f/fxtal(nom)
Typical external fundamental crystal characteristics (see Section 10.1) Parameter MHz[1] 3rd harmonics 32.11 100 MHz ppm nominal crystal frequency nominal crystal frequency deviation load capacitance series resistance shunt capacitance 3rd harmonics fundamental 3rd harmonics fundamental 3rd harmonics fundamental
[2] [2]
Conditions
Min
Typ
Max
Unit
Crystal oscillator for 32.11
Crystal specification (X1) CL Rs C0 24.576 8 8 50 60 4.3 3.3 70 pF pF pF pF MHz ppm
Crystal oscillator for 24.576 MHz[1] fxtal(nom) f/fxtal(nom) nominal crystal frequency nominal crystal frequency deviation load capacitance series resistance shunt capacitance 3rd harmonics fundamental Rs C0 3rd harmonics fundamental 3rd harmonics fundamental
[1] [2] The crystal oscillator drive level is typical 0.28 mW. Effect from C0 excluded.
[2] [2]
3rd harmonics
Crystal specification (X1) CL 40 10 20 80 60 3.5 7 pF pF pF pF
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10. Application information
10.1 Oscillator applications
10.1.1 Generic oscillator applications
Figure 5 shows the generic oscillator circuit with quartz crystals and with direct clock input. Table 9 shows configuration examples for different quartz crystals.
SAF7115
D1 (7) XTALI
fxtal(nom)
C1 (6) XTALO
Rs
SAF7115
D1 (7) XTALI
32.11 MHz or 24.576 MHz
C1 (6) XTALO
L C2 C1 C3
n.c.
clock
001aah884
001aah706
a. Generic oscillator circuit Fig 5. Oscillator applications (see Table 9) Table 9. Example 1 2 3 4 5
[1] [2]
b. With direct clock.
Configuration examples quartz crystal (see Figure 5) Quartz crystal[1] Type 3rd harmonic 3rd harmonic fundamental fundamental fundamental fxtal(nom) (MHz) CL (pF) 32.11 24.576 32.11 32.11 24.576 8 8 20 8 8 Oscillator circuit L (H) 4.7 4.7 none none none C1 (nF) 1 1 none none none C2 (pF) 15 18 33 10 15 C3 (pF) 15 18 33 10 15 Rs ()[2] 0 0 0 0 0
See Table 8. See Section 10.1.2.
10.1.2 Fundamental quartz crystals with restricted drive level
Leave out L and C1 when using fundamental quartz crystal and restricted drive level (see Section 10.1.1). Use a series resistance Rs at pin XTALO, when the internal oscillator of the SAF7115 provides too much power Pdrive to the selected quartz crystal. Note that the decreased crystal amplitude results in a lower drive level, but on the other hand the jitter performance will decrease.
10.2 PCB layout guidelines for oscillator applications
Place the quartz crystal on the PCB as close to pins XTALI and XTALO as possible to minimize susceptibility to noise from current loops. Minimize parasitic capacitances.
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11. Test information
11.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for use in automotive applications.
11.2 Boundary scan test
The SAF7115 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAF7115 follows the IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture set by the Joint Test Action Group (JTAG). The 5 dedicated pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST_N), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 10). Details about the JTAG BST-TEST can be found in specification IEEE Std. 1149.1.
Table 10. BYPASS EXTEST SAMPLE BST instructions supported by the SAF7115 this mandatory instruction provides a minimum length serial path (1-bit) between TDI and TDO when no test operation of the component is required this mandatory instruction allows testing of off-chip circuitry and board level interconnections this mandatory instruction can be used to take a sample of the inputs during normal operation of the component; it can also be used to preload data values into the latched outputs of the boundary scan register this optional instruction is useful for testing when not all ICs have BST; this instruction addresses the bypass register while the boundary scan register is in external test mode this optional instruction will provide information on the components manufacturer, part number and version number
Instruction Description
CLAMP
IDCODE
11.2.1 Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in the functional mode. The reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To compensate for the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST_N pin LOW.
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11.2.2 Device identification codes
A device identification register is specified in IEEE Std. 1149.1b-1994. It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and the determination of the version number of ICs during field service. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can be subsequently shifted out. This code can be used at board level to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Figure 6.
MSB 31 28 27 TDI
12 11 00000010101 11-bit manufacturer identification
1
LSB 0 1 TDO
nnnn 0111 0001 0001 0101 4-bit version code 16-bit part number
001aag284
Fig 6.
32 bits of identification code
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12. Package outline
HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad
SOT638-1
c y exposed die pad side X Dh 75 76 51 50 ZE
A
e E HE wM bp pin 1 index Lp L detail X
Eh
A
A2
A1
(A3)
100 1 wM ZD 25 bp D HD
26
e
vM A B vM B
0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 14.1 13.9 Dh 7.1 6.1 E(1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD
10 mm
HE
L 1
Lp 0.75 0.45
v 0.2
w 0.08
y 0.08
ZD(1) ZE(1) 1.15 0.85 1.15 0.85
7 0
16.15 16.15 15.85 15.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 05-02-02
Fig 7.
SAF7115_1
Package outline HTQFP100 (SOT638-1)
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TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls
SOT1016-1
D
B
A
ball A1 index area A2 A1 detail X
E
A
e1 e 1/2 e b v w
M M
CAB C
C y1 C y
ball A1 index area
P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14
e
e2 1/2 e
X
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.2 A1 0.4 0.3 A2 0.80 0.65 b 0.5 0.4 D 12.1 11.9 E 12.1 11.9 e 0.8 e1 10.4 e2 10.4 v 0.15 w 0.05 y 0.08 y1 0.1
OUTLINE VERSION SOT1016-1
REFERENCES IEC JEDEC --JEITA
EUROPEAN PROJECTION
ISSUE DATE 07-06-20 07-07-27
Fig 8.
SAF7115_1
Package outline TFBGA160 (SOT1016-1)
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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 9) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12
Table 11. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 12. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 9.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 9.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 13. Acronym ACC ADC AEC AGC BCS CC CCST CGC CGMS CMOS CVBS DC EIA ESD FIFO IC I2C-bus IEEE I/O
SAF7115_1
Abbreviations Description Automatic Clamp Control Analog-to-Digital Converter Automotive Electronic Council Automatic Gain Control Brightness Contrast Saturation Close Caption Chinese Character System Teletext Clock Generation Circuit Copy Generation Management System Complementary MOS Composite Video Blanking Sync[1] Directed Current Electronic Industries Alliance ElectroStatic Discharge First In First Out Integrated Circuit Inter-IC-bus Institute of Electrical and Electronics Engineers Input/Output
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Abbreviations ...continued Description International Telecommunication Union Joint Test Action Group Line-Locked Clock Least Significant Bit Metal-Oxide-Semiconductors Most Significant Bit MUltipleXer North-American Broadcast Text System National Television Systems Committee Phase Alternating Line Printed Circuit Board Phase-Locked Loop Real Time Real Time Control Systeme Electronique Coleur Avec Memoire (French color TV standard) Surface Mount Device Test Access Port Transistor-Transistor Logic TeleVision United States of america Vertical Blanking Interval Video Cassette Recorder Video Graphics Array Vertical Interval Time Code Video Program System Video Tape Recorder Wide Screen Signalling World System Teletext
Table 13. Acronym ITU JTAG LLC LSB MOS MSB MUX NABTS NTSC PAL PCB PLL RT RTC SECAM SMD TAP TTL TV US VBI VCR VGA VITC VPS VTR WSS WST
[1]
CVBS is also known as "composite video signal".
15. Glossary
Arbiter -- Electronic means to allocate access to shared resources. H-port -- Digital host port for CbCr video input or output. I-port -- Digital image port for scaled video data output. Macrovision copy protection -- The SAF7115 includes Macrovision detection only. Moji -- Japanese teletext. Moji means character. X-port -- Digital video expansion port (X-port), for unscaled digital video input and output. Y/C -- Luminance and separated modulated chrominance video signal. YCbCr -- Digital color coding format.
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16. References
[1]
SAF7115 User Manual; please contact your local sales office (see Section 19).
17. Revision history
Table 14. Revision history Release date 20081015 Data sheet status Product data sheet Change notice Supersedes Document ID SAF7115_1
SAF7115_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
29 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
18.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
18.4 Licenses
Purchase of NXP ICs with Macrovision copyright protection technology This product incorporates copyright protection technology that is protected by claims of U.S. Patent Nos. 5583936, 6516132, 6836549, 7050698 ("Encoder Devices") or U.S. Patent No. 6600873 ("Detection Devices") and other intellectual property rights owned by Macrovision Corporation and other rights owners. The Encoder Devices may only be purchased by buyers who, according to information supplied by Macrovision Corporation to NXP Semiconductors, have a valid license obtained from Macrovision Corporation, 2830 De La Cruz Boulevard, Santa Clara CA 95050, USA. Tel: +1 (408) 562-8400, Fax: +1 (408) 567-1800. Use of this copyright protection technology is intended for home and other limited viewing uses only, unless otherwise authorized by Macrovision Corporation. Reverse engineering or disassembly is prohibited.
18.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
SAF7115_1 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
30 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
20. Index
A
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Adaptive comb filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 2 Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 9 Analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 9 Analog part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Analog supply voltages . . . . . . . . . . . . . . . . . . . . . . . . .8, 14 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . .14 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Audio clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2, 5, 9 Automatic detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Automatic field detection . . . . . . . . . . . . . . . . . . . . . . . . . .2 Automatic recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General industrial video applications . . . . . . . . . . . . . . . . . 4
H
Horizontal PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Host port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 12, 18 H-port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 12, 18
I
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 5, 15 Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Image port . . . . . . . . . . . . . . . . . . . . . . . . 1, 3, 5, 10, 16, 18 In-car entertainment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 4 In-car navigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 4 In-car TV reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 In-car video reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 9, 14 I-port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 3, 5, 10, 16, 18
B
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Boundary scan test . . . . . . . . . . . . . . . . . . . . . . . . .5, 10, 21 Brightness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 Broadcast standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
L
Line-Locked Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 10 Luminance and chrominance processing . . . . . . . . . . . . . 2
C
Chrominance/luminance separation . . . . . . . . . . . . . . . . . .1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 10 Comb filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 2 Configuration examples quartz crystal . . . . . . . . . . . . . . .20 Contrast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 Conversion to square pixel format . . . . . . . . . . . . . . . . . . .3 Crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
M
Multistandard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 2, 3
N
Navigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 20
O
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Oscillator applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
D
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Digital input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 15 Digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 15 Digital supply voltages . . . . . . . . . . . . . . . . . . . . . . . . .9, 14 Direct clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
P
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4, 6, 23, 24 PCB footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 24 PCB layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . 13, 20 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 4, 5, 15, 16 Programmable gain control . . . . . . . . . . . . . . . . . . . . . . . . 2 Programmable sharpness control . . . . . . . . . . . . . . . . . . . 3 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Programming registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Programming set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
E
Expansion port . . . . . . . . . . . . . . . . . . .1, 2, 3, 5, 11, 16, 18 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
F
Field detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23, 24 Fundamental crystal . . . . . . . . . . . . . . . . . . . . . . . . . .19, 20
Q
Quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 20
G
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 9
R
Read-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 4
continued >>
SAF7115_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
31 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
Real time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 4 Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
S
Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3, 5 Sharpness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Square pixel clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Square pixel format . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 Subcarrier PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8, 14
T
Teletext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3, 5 Test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 10 TV applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 TV standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
U
User manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
V
Variable zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 VBI capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 VBI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 VBI data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Video acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Video applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Video capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Video processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 5 Video reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Videotext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
W
Wide screen signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 World standard teletext . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
X
X-port . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 2, 3, 11, 16, 18
Z
Zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
SAF7115_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
32 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
21. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Pin allocation table (HTQFP100) . . . . . . . . . . . .6 Pin allocation table (TFBGA160)[1] . . . . . . . . . .7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .13 Thermal characteristics . . . . . . . . . . . . . . . . . .13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .14 Typical external fundamental crystal characteristics (see Section 10.1) . . . . . . . . . .19 Configuration examples quartz crystal (see Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . .20 BST instructions supported by the SAF7115 . .21 SnPb eutectic process (from J-STD-020C) . . .26 Lead-free process (from J-STD-020C) . . . . . .26 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .27 Revision history . . . . . . . . . . . . . . . . . . . . . . . .29
SAF7115_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
33 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
22. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6 X-port input and output timing . . . . . . . . . . . . . . .18 I-port output timing, also valid for IX-port and H-port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Oscillator applications (see Table 9) . . . . . . . . . .20 32 bits of identification code. . . . . . . . . . . . . . . . .22 Package outline HTQFP100 (SOT638-1). . . . . . .23 Package outline TFBGA160 (SOT1016-1). . . . . .24 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SAF7115_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 15 October 2008
34 of 35
NXP Semiconductors
SAF7115
Multistandard video decoder
23. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Video acquisition. . . . . . . . . . . . . . . . . . . . . . . . 2 Comb filter video decoder. . . . . . . . . . . . . . . . . 2 Video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 VBI data slicer. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Clock generation. . . . . . . . . . . . . . . . . . . . . . . . 4 General features . . . . . . . . . . . . . . . . . . . . . . . . 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal characteristics. . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 20 Oscillator applications. . . . . . . . . . . . . . . . . . . 20 Generic oscillator applications . . . . . . . . . . . . 20 Fundamental quartz crystals with restricted drive level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.2 PCB layout guidelines for oscillator applications. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 21 11.1 Quality information . . . . . . . . . . . . . . . . . . . . . 21 11.2 Boundary scan test. . . . . . . . . . . . . . . . . . . . . 21 11.2.1 Initialization of boundary scan circuit . . . . . . . 21 11.2.2 Device identification codes . . . . . . . . . . . . . . . 22 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 13 Soldering of SMD packages . . . . . . . . . . . . . . 25 13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 25 13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 25 13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 15 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.4 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1 2 2.1 2.2 2.3 2.4 2.5 2.6 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.1.1 10.1.2 18.5 19 20 21 22 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 33 34 35
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 October 2008 Document identifier: SAF7115_1

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